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d8b3b76bcd
* gnu/packages/hdl.scm (open-logic): Update to 4.4.0. [native-inputs]: Add python-jinja2 and python-scipy. [arguments]: Setenv HOME in ’check #:phase. Merges guix/guix!6786 Change-Id: Ia575bc8d0bd09cfb5c84e9047d8e48bf25ab9c31
201 lines
7.6 KiB
Scheme
201 lines
7.6 KiB
Scheme
;;; GNU Guix --- Functional package management for GNU
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;;; Copyright © 2026 Cayetano Santos <csantosb@inventati.org>
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;;;
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;;; This file is part of GNU Guix.
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;;;
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;;; GNU Guix is free software; you can redistribute it and/or modify it
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;;; under the terms of the GNU General Public License as published by
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;;; the Free Software Foundation; either version 3 of the License, or (at
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;;; your option) any later version.
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;;;
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;;; GNU Guix is distributed in the hope that it will be useful, but
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;;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;;; GNU General Public License for more details.
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;;;
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;;; You should have received a copy of the GNU General Public License
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;;; along with GNU Guix. If not, see <http://www.gnu.org/licenses/>.
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(define-module (gnu packages hdl)
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#:use-module ((guix licenses) #:prefix license:)
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#:use-module (guix build-system copy)
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#:use-module (guix gexp)
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#:use-module (guix git-download)
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#:use-module (guix packages)
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#:use-module (gnu packages electronics)
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#:use-module (gnu packages python)
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#:use-module (gnu packages python-science)
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#:use-module (gnu packages python-xyz))
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(define-public ieee-p1076
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(package
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(name "ieee-p1076")
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(version "2019")
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(source
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(origin
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(method git-fetch)
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(uri (git-reference
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(url "https://opensource.ieee.org/vasg/Packages/")
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(commit (string-append "1076-" version))))
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(file-name (git-file-name name version))
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(sha256
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(base32 "1va626i5ww2ziw3dghw0d2mq7mrj5dwcn0h019h77866yw2pq9xn"))))
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(build-system copy-build-system)
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(native-inputs (list python-minimal-wrapper nvc python-vunit))
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(arguments
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(list
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;; Not all 2019 features are supported by nvc compiler.
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;; pass 1055 of 1648
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#:tests? #f
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#:install-plan
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#~'(("ieee" "share/ieee-p1076/ieee" #:include ("vhdl"))
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("std" "share/ieee-p1076/std" #:include ("vhdl")))))
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(native-search-paths
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(list (search-path-specification
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(variable "FW_IEEE_p1076")
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(separator #f)
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(files (list "share/ieee-p1076")))))
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(home-page "https://IEEE-P1076.gitlab.io")
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(synopsis "VHDL libraries corresponding to the IEEE 1076 standard")
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(description
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"Open source materials intended for reference by the IEEE standard 1076,
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as approved and published by the @acronym{VHDL, Very High Speed Hardware
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Description Language} Analysis and Standardization Group.")
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(license license:asl2.0)))
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(define-public neorv32
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(package
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(name "neorv32")
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(version "1.12.7")
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(source
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(origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/stnolting/neorv32")
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(commit (string-append "v" version))))
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(file-name (git-file-name name version))
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(sha256
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(base32
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"030djnf5ww4b2w6lhb9lpprq2iawf8v93rmmgfgnbr56k4blyyk6"))))
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(outputs
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'("out" "neorv32"))
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(build-system copy-build-system)
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(arguments
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(list
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#:tests? #f ;FIXME: nvc checksum errors inside the build env
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#:phases
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#~(modify-phases %standard-phases
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(add-after 'install 'check
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(lambda* (#:key tests? #:allow-other-keys)
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(when tests?
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(substitute* '("rtl/file_list_cpu.f" "rtl/file_list_soc.f")
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(("NEORV32_RTL_PATH_PLACEHOLDER") "rtl"))
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(for-each
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(lambda (f)
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(invoke
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"sh" "-c"
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(format #f "cat rtl/~a.f | xargs nvc --work=neorv32 -a" f)))
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'("file_list_soc" "file_list_cpu"))
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(for-each
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(lambda (f)
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(invoke "nvc" "--work=neorv32" "-a" f))
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`("sim/sim_uart_rx.vhd"
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,@(find-files "sim" "x.*\\.vhd$")
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"sim/neorv32_tb.vhd"))
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(invoke "nvc" "--work=neorv32" "-e" "neorv32_tb")
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(invoke "nvc" "--work=neorv32" "-r" "--stop-time=10ms"
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"neorv32_tb")))))
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#:install-plan
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#~'(("rtl" "share/neorv32/work/rtl"
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#:exclude-regexp (".*\\.f$" ".*\\.sh$"))
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("rtl" "share/neorv32/neorv32/rtl"
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#:exclude-regexp (".*\\.f$" ".*\\.sh$")
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#:output "neorv32"))))
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(native-inputs (list nvc))
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(native-search-paths
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(list (search-path-specification
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(variable "FW_NEORV32")
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(separator #f)
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(files (list "share/neorv32")))))
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(home-page "https://stnolting.github.io/neorv32/")
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(synopsis "RISC-V soft core CPU in VHDL")
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(description
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"Neorv32 is a small, customizable 32 bits microcontroller-like system on
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chip written in platform-independent VHDL.")
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(properties
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`((output-synopsis "out" "Instance this design library as work")
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(output-synopsis "neorv32" "Instance this design library as neorv32")))
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(license license:bsd-3)))
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(define-public open-logic
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(package
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(name "open-logic")
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(version "4.4.0")
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(source
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(origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/open-logic/open-logic/")
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(commit version)
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;; Required by the en_cl_fix submodule.
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(recursive? #t)))
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(file-name (git-file-name name version))
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(sha256
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(base32
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"01kxrglbq50v73796iq9a1vi68i8k2wykk7gga9847smfznqwjwr"))))
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(outputs
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'("out" "olo"))
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(properties
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`((output-synopsis "out" "Instance this design library as work")
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(output-synopsis "olo" "Instance this design library as olo")))
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(build-system copy-build-system)
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(arguments
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(list
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#:phases
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#~(modify-phases %standard-phases
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(add-after 'install 'check
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(lambda* (#:key tests? inputs #:allow-other-keys)
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(when tests?
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(setenv "HOME" "/tmp")
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(with-directory-excursion "3rdParty/en_cl_fix/sim"
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(invoke "python3" "run.py" "--simulator" "nvc"
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"--simulator-path"
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(dirname (search-input-file inputs "bin/nvc"))))
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(with-directory-excursion "sim"
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(substitute* "run.py"
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;; This is required to comply with current VUnit, see:
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;; https://github.com/VUnit/vunit/issues/777
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(("compile_builtins=False, ")
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""))
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(invoke "python3" "run.py" "--nvc" "-v"))))))
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#:install-plan
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#~'(;; Library work.
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("src" "share/open-logic/work/src"
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#:include ("vhd"))
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("3rdParty" "share/open-logic/work/3rdParty"
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#:include ("vhd"))
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;; Library olo.
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("src" "share/open-logic/olo/src"
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#:include ("vhd") #:output "olo")
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("3rdParty" "share/open-logic/olo/3rdParty"
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#:include ("vhd") #:output "olo"))))
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(native-inputs
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(list nvc
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python-jinja2
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python-matplotlib
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python-minimal
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python-scipy
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python-vunit))
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(native-search-paths
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(list (search-path-specification
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(variable "FW_OPEN_LOGIC")
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(separator #f)
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(files (list "share/open-logic")))))
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(home-page "https://github.com/open-logic/open-logic/")
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(synopsis "Open library of VHDL standard components")
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(description "Open Logic implements commonly used design units in a
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reusable and vendor/tool-independent way. It is written following the VHDL
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2008 standard, but can also be used from System Verilog.")
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(license (list license:lgpl2.1
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license:expat)))) ;en_cl_fix uses Expat license
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